Along the progress in higher and multiple performances of an information equipment and the like in recent years, a system LSI, a SoC and other devices are widely used in portable information equipment, personal computers and so forth. The system LSI is configured to integrate multiple system functions on a single chip. The SoC is configured to integrate a memory, a logic circuit, and an analog circuit into a single chip. Such a system LSI or a SoC, which is designed in a large scale and configured to operate at a high speed, uses techniques called DFT (design for testability) such as scan test method or a BIST (built-in self test) method, in order to suppress testing costs, for example. Japanese Patent Application Laid-open Publication No. 2002-124852 discloses the scan test method. In the scan test method, a flip-flop is replaced by a scan flip-flop. It is possible to give scan-in data from outside the system LSI or the SoC and to read the test values through an external input-output terminal by using the scan flip-flop. Accordingly, it is easier to produce a test pattern using an ATPG (automatic test pattern generator).
In the above-mentioned scan test method, when a scan test is performed for a logic circuit unit including a clock frequency divider to which clock signals are to be inputted, a multiplexer is provided on an output end of the clock frequency divider. A delay test using a multiplexer for selecting a clock signal or a divided clock signal has a problem that generation of a scan pattern becomes extremely inefficient which depends on an operating frequency. Moreover, the delay test has another problem that timing adjustment is difficult to make due to a skew between the clock signal and the divided clock signal.